Verification Engineer
Verify next-generation RISC-V processors in Barcelona using SystemVerilog, UVM, formal and dynamic methods, with flexible work, career growth, and visa support.
As a Senior Verification Engineer, you will work within the Verification Team and play a crucial role in ensuring the correctness and functionality of complex digital designs at the Register Transfer Level according to the specification, using advanced verification methodologies and tools to validate the designs.
Requirements
Master or PhD
English C1
Industrial experience +8 years
Proficiency in SystemVerilog and UVM
Knowledge of scripting languages (Python, Perl, Bash, TCL) and regression tools
Experience with simulation and simulation tools
Knowledge of revision control methodology and tools (git, svn)
Experience in block level and sub-system or top level verification
Experience with formal and dynamic verification
Strong problem-solving skills and attention to detail
Excellent communication and teamwork abilities
Why Semidynamics?
Work at one of Europe's most promising deep-tech semiconductor scale-ups.
Accelerated development path.
4 days per week in the Barcelona office (city center), 1 WFH.
1 week of work from everywhere in the world.
Competitive package.
A collaborative, technical, and growth-oriented environment that values direct ownership and clear thinking.
- Department
- Silicon Engineering
- Location
- Barcelona
- Employment type
- Full-time